<?xml version="1.0"?>
<feed xmlns="http://www.w3.org/2005/Atom" xml:lang="de">
	<id>https://wiki.uugrn.org/index.php?action=history&amp;feed=atom&amp;title=Geschichte%2FServer%2Ftop3%2Fpciconf</id>
	<title>Geschichte/Server/top3/pciconf - Versionsgeschichte</title>
	<link rel="self" type="application/atom+xml" href="https://wiki.uugrn.org/index.php?action=history&amp;feed=atom&amp;title=Geschichte%2FServer%2Ftop3%2Fpciconf"/>
	<link rel="alternate" type="text/html" href="https://wiki.uugrn.org/index.php?title=Geschichte/Server/top3/pciconf&amp;action=history"/>
	<updated>2026-04-29T10:14:54Z</updated>
	<subtitle>Versionsgeschichte dieser Seite in UUGRN</subtitle>
	<generator>MediaWiki 1.42.5</generator>
	<entry>
		<id>https://wiki.uugrn.org/index.php?title=Geschichte/Server/top3/pciconf&amp;diff=13460&amp;oldid=prev</id>
		<title>Sdk: Sdk verschob die Seite UUGRN:Server/top3/pciconf nach Geschichte/Server/top3/pciconf</title>
		<link rel="alternate" type="text/html" href="https://wiki.uugrn.org/index.php?title=Geschichte/Server/top3/pciconf&amp;diff=13460&amp;oldid=prev"/>
		<updated>2022-04-09T14:46:56Z</updated>

		<summary type="html">&lt;p&gt;Sdk verschob die Seite &lt;a href=&quot;/UUGRN:Server/top3/pciconf&quot; class=&quot;mw-redirect&quot; title=&quot;UUGRN:Server/top3/pciconf&quot;&gt;UUGRN:Server/top3/pciconf&lt;/a&gt; nach &lt;a href=&quot;/Geschichte/Server/top3/pciconf&quot; title=&quot;Geschichte/Server/top3/pciconf&quot;&gt;Geschichte/Server/top3/pciconf&lt;/a&gt;&lt;/p&gt;
&lt;table style=&quot;background-color: #fff; color: #202122;&quot; data-mw=&quot;interface&quot;&gt;
				&lt;tr class=&quot;diff-title&quot; lang=&quot;de&quot;&gt;
				&lt;td colspan=&quot;1&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;← Nächstältere Version&lt;/td&gt;
				&lt;td colspan=&quot;1&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;Version vom 9. April 2022, 14:46 Uhr&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-notice&quot; lang=&quot;de&quot;&gt;&lt;div class=&quot;mw-diff-empty&quot;&gt;(kein Unterschied)&lt;/div&gt;
&lt;/td&gt;&lt;/tr&gt;&lt;/table&gt;</summary>
		<author><name>Sdk</name></author>
	</entry>
	<entry>
		<id>https://wiki.uugrn.org/index.php?title=Geschichte/Server/top3/pciconf&amp;diff=9941&amp;oldid=prev</id>
		<title>Rabe: neu</title>
		<link rel="alternate" type="text/html" href="https://wiki.uugrn.org/index.php?title=Geschichte/Server/top3/pciconf&amp;diff=9941&amp;oldid=prev"/>
		<updated>2013-03-25T21:41:35Z</updated>

		<summary type="html">&lt;p&gt;neu&lt;/p&gt;
&lt;p&gt;&lt;b&gt;Neue Seite&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&amp;lt;!-- update in vim: &lt;br /&gt;
:r !ssh top3.uugrn.org pciconf -lv&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
hostb0@pci0:0:0:0:	class=0x060000 card=0x200a8086 chip=0x01008086 rev=0x09 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;2nd Generation Core Processor Family DRAM Controller&amp;#039;&lt;br /&gt;
    class      = bridge&lt;br /&gt;
    subclass   = HOST-PCI&lt;br /&gt;
pcib1@pci0:0:1:0:	class=0x060400 card=0x200a8086 chip=0x01018086 rev=0x09 hdr=0x01&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port&amp;#039;&lt;br /&gt;
    class      = bridge&lt;br /&gt;
    subclass   = PCI-PCI&lt;br /&gt;
vgapci0@pci0:0:2:0:	class=0x030000 card=0x200a8086 chip=0x01028086 rev=0x09 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;2nd Generation Core Processor Family Integrated Graphics Controller&amp;#039;&lt;br /&gt;
    class      = display&lt;br /&gt;
    subclass   = VGA&lt;br /&gt;
none0@pci0:0:22:0:	class=0x078000 card=0x200a8086 chip=0x1c3a8086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;6 Series/C200 Series Chipset Family MEI Controller&amp;#039;&lt;br /&gt;
    class      = simple comms&lt;br /&gt;
atapci0@pci0:0:22:2:	class=0x010185 card=0x200a8086 chip=0x1c3c8086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;6 Series/C200 Series Chipset Family IDE-r Controller&amp;#039;&lt;br /&gt;
    class      = mass storage&lt;br /&gt;
    subclass   = ATA&lt;br /&gt;
uart2@pci0:0:22:3:	class=0x070002 card=0x200a8086 chip=0x1c3d8086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;6 Series/C200 Series Chipset Family KT Controller&amp;#039;&lt;br /&gt;
    class      = simple comms&lt;br /&gt;
    subclass   = UART&lt;br /&gt;
em0@pci0:0:25:0:	class=0x020000 card=0x200a8086 chip=0x15028086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;82579LM Gigabit Network Connection&amp;#039;&lt;br /&gt;
    class      = network&lt;br /&gt;
    subclass   = ethernet&lt;br /&gt;
ehci0@pci0:0:26:0:	class=0x0c0320 card=0x200a8086 chip=0x1c2d8086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;6 Series/C200 Series Chipset Family USB Enhanced Host Controller&amp;#039;&lt;br /&gt;
    class      = serial bus&lt;br /&gt;
    subclass   = USB&lt;br /&gt;
ehci1@pci0:0:29:0:	class=0x0c0320 card=0x200a8086 chip=0x1c268086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;6 Series/C200 Series Chipset Family USB Enhanced Host Controller&amp;#039;&lt;br /&gt;
    class      = serial bus&lt;br /&gt;
    subclass   = USB&lt;br /&gt;
pcib2@pci0:0:30:0:	class=0x060401 card=0x200a8086 chip=0x244e8086 rev=0xa4 hdr=0x01&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;82801 PCI Bridge&amp;#039;&lt;br /&gt;
    class      = bridge&lt;br /&gt;
    subclass   = PCI-PCI&lt;br /&gt;
isab0@pci0:0:31:0:	class=0x060100 card=0x200a8086 chip=0x1c4e8086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;Q67 Express Chipset Family LPC Controller&amp;#039;&lt;br /&gt;
    class      = bridge&lt;br /&gt;
    subclass   = PCI-ISA&lt;br /&gt;
ahci0@pci0:0:31:2:	class=0x010601 card=0x200a8086 chip=0x1c028086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;6 Series/C200 Series Chipset Family 6 port SATA AHCI Controller&amp;#039;&lt;br /&gt;
    class      = mass storage&lt;br /&gt;
    subclass   = SATA&lt;br /&gt;
none1@pci0:0:31:3:	class=0x0c0500 card=0x200a8086 chip=0x1c228086 rev=0x04 hdr=0x00&lt;br /&gt;
    vendor     = &amp;#039;Intel Corporation&amp;#039;&lt;br /&gt;
    device     = &amp;#039;6 Series/C200 Series Chipset Family SMBus Controller&amp;#039;&lt;br /&gt;
    class      = serial bus&lt;br /&gt;
    subclass   = SMBus&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;/div&gt;</summary>
		<author><name>Rabe</name></author>
	</entry>
</feed>